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A6173081 Series Preliminary Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 128K X 8 BIT HIGH SPEED CMOS SRAM History Initial issue Issue Date July 14, 2000 Remark Preliminary PRELIMINARY (July, 2000, Version 0.0) AMIC Technology, Inc. A6173081 Series Preliminary Features n n n n Center power pinout Supply voltage: 5V10% Access times: 12/15 ns (max.) Current: Operating: -12: 170mA (max.) -15: 165mA (max.) Standby: TTL: 25mA (max.) CMOS: 8mA (max.) n n n n n Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 3V (min.) Available in 32-pin 300mil / 400mil SOJ packages 128K X 8 BIT HIGH SPEED CMOS SRAM General Description The A6173081 is a high-speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a 5V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 3V. Pin Configurations n SOJ A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 32 31 30 29 28 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 A6173081S(SW) 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 PRELIMINARY (July, 2000, Version 0.0) 1 AMIC Technology, Inc. A6173081 Series Block Diagram A0 ADDRESS DECODER A16 1,048,576-BIT MEMORY ARRAY I/O0 - I/O7 8 I/O CONTROL 8 8 WE OE CE CONTROL LOGIC Pin Descriptions - SOJ Pin No. 1-4, 13-21, 29-32 6-7, 10-11, 22-23, 26-27 5 28 12 8, 24 9, 25 Symbol A0 - A16 I/O0 - I/O7 Description Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground CE OE WE VCC GND PRELIMINARY (July, 2000, Version 0.0) 2 AMIC Technology, Inc. A6173081 Series Recommended DC Operating Conditions (TA = 0C to + 70C) Symbol VCC GND VIH VIL CL Parameter Supply Voltage Ground Input High Voltage Input Low (1) Voltage Output Load Min. 4.5 0 2.2 -0.5 Typ. 5.0 0 0 Max. 5.5 0 VCC + 0.5 +0.8 30 Unit V V V V pF Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0C to +70C Storage Temperature, Tstg . . . . . . . . . . -55C to +125C Temperature Under Bias, Tbias . . . . . . . . -10C to +85C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = 0C to + 70C, VCC = 5V 10%, GND = 0V) A6173081-12 Min. Max. 2 2 A6173081-15 Min. Max. 2 2 A A VIN = GND to VCC CE = VIH, OE = VIH VI/O = GND to VCC CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% CE = VIH CE VCC - 0.2V, VIN VCC -0.2V or VIN 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions ILI ILO Input Leakage Output Leakage - ICC1 (2) ISB Dynamic Operating Current - 170 25 - 165 25 mA mA ISB1 VOL VOH Standby Power Supply Current Output Low Voltage Output High Voltage 2.4 8 0.4 - 2.4 8 0.4 - mA V V Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. PRELIMINARY (July, 2000, Version 0.0) 3 AMIC Technology, Inc. A6173081 Series Truth Table Mode Standby Output Disable Read Write Note: X = H or L CE H L L L OE WE I/O Operation High Z High Z DOUT DIN Supply Current ISB, ISB1 ICC1 ICC1 ICC1 X H L X X H H L Capacitance (TA = 25C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 8 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0C to +70C, VCC = 5V 10%) Symbol Parameter A6173081-12 Min. Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable Output in High Z Output Disable to Output in High Z Output Hold from Address Change 12 3 0 0 0 3 12 12 6 6 6 15 3 0 0 3 15 15 8 8 8 ns ns ns ns ns ns ns ns ns Max. A6173081-15 Min. Max. Unit PRELIMINARY (July, 2000, Version 0.0) 4 AMIC Technology, Inc. A6173081 Series AC Characteristics (continued) Symbol Parameter A6173081-12 Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 12 10 0 10 10 0 0 6 0 3 6 15 12 0 12 12 0 0 7 0 3 8 ns ns ns ns ns ns ns ns ns ns Max. A6173081-15 Min. Max. Unit Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address tAA OE tOE tOLZ5 CE tACE tCLZ5 DOUT tOH tOHZ5 tCHZ5 PRELIMINARY (July, 2000, Version 0.0) 5 AMIC Technology, Inc. A6173081 Series Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 3(1, 3, 4,) CE tACE tCLZ5 tCHZ5 DOUT Notes: 1. 2. 3. 4. 5. WE is high for Read Cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured 200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (July, 2000, Version 0.0) 6 AMIC Technology, Inc. A6173081 Series Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address tAW tCW 5 CE tAS1 (4) tWP 2 tWR 3 WE tDW tDH DIN tWHZ 7 tOW 7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE (4) tCW 5 tWR 3 tWP 2 WE tDW DIN tDH tWHZ 7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low WE . tWR is measured from the earliest of CE or WE going high to the end of the Write cycle If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured 200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (July, 2000, Version 0.0) 7 AMIC Technology, Inc. A6173081 Series AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 5V 480 OUTPUT ZO=50 RL=50 VT=1.5V * Including scope and jig. DATAOUT 5pF* 255 Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0C to 70C) Symbol VDR Parameter VCC for Data Retention Min. 3 Max. 5.5 Unit V Conditions CE VCC - 0.2V ICCDR Data Retention Current - 1 mA VCC = 3.0V CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V tCDR tR Chip Disable to Data Retention Time Operation Recovery Time 0 TRC* - ns See Retention Waveform ms tRC = Read Cycle Time PRELIMINARY (July, 2000, Version 0.0) 8 AMIC Technology, Inc. A6173081 Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR VDR > 3.0V 4.5V tR CE VIH CE > VDR - 0.2V VIH Ordering Information Part No. A6173081S-12 12 A6173081SW-12 A6173081S-15 15 A6173081SW-15 165 8 32L 400mil SOJ 170 8 32L 400mil SOJ 32L 300mil SOJ Access Time (ns) Operating Current Max. (mA) CMOS Standby Max. (mA) Package 32L 300mil SOJ PRELIMINARY (July, 2000, Version 0.0) 9 AMIC Technology, Inc. A6173081 Series Package Information SOJ 32L(300mil) Outline Dimensions unit: inches/mm D 32 17 1 16 E1 E A2 C A y E2 y S Seating Plane D Symbol A A1 A2 b b1 C D E E1 E2 e S y Dimensions in inches Min 0.128 0.052 0.095 0.016 0.026 0.006 0.820 0.330 0.295 0.260 Nom 0.132 0.100 0.018 0.028 0.008 0.825 0.335 0.300 0.267 0.050 Max 0.140 0.105 0.020 0.032 0.012 0.830 0.340 0.305 0.274 0.048 0.004 Min 0.025" y b b1 e 0.004 Dimensions in mm Min 3.25 2.08 2.41 0.41 0.66 0.15 20.83 8.39 7.49 6.61 Nom 3.35 2.54 0.46 0.71 0.20 20.96 8.51 7.62 6.78 1.27 Max 3.56 2.67 0.51 0.81 0.30 21.08 8.63 7.75 6.96 1.22 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. A1 PRELIMINARY (July, 2000, Version 0.0) 10 AMIC Technology, Inc. A6173081 Series Package Information SOJ 32L (400mil) Outline Dimensions unit: inches/mm D 32 17 1 16 E1 E A2 C A y A1 S Seating Plane Min 0.025" y b b1 e D E2 0.004 y Symbol A A1 A2 b b1 C D E E1 E2 e S y Dimensions in inches Min 0.131 0.082 0.105 0.016 0.026 0.006 0.820 0.435 0.395 0.360 -5 Nom 0.138 0.110 0.018 0.028 0.008 0.825 0.440 0.400 0.370 0.050 2 Max 0.145 0.115 0.020 0.032 0.011 0.830 0.445 0.405 0.380 0.045 0.004 6 Dimensions in mm Min 3.33 2.08 2.67 0.41 0.66 0.15 20.83 11.05 10.03 9.15 -5 Nom 3.51 2.79 0.46 0.71 0.20 20.96 11.18 10.16 9.40 1.27 2 Max 3.68 2.91 0.51 0.81 0.28 21.08 11.31 10.29 9.65 1.14 0.10 6 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (July, 2000, Version 0.0) 11 AMIC Technology, Inc. |
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